1. Field of the Invention
The present invention relates to a method for fabricating a transistor, and more particularly to a method for fabricating an asymmetrical lightly doped drain transistor.
2. Description of the Prior art
In scaling a MOSFET down to deep submicron, a short channel effect may occur. For eliminating such short channel effect, there have been conventionally proposed various methods such as a method of forming source/drain regions with a shallow junction, a method of forming a gate electrode with a small thickness, and a deep channel implantation method of deeply implanting channel ions in a substrate.
These methods can solve the short channel effect occurring in deep submicron MOSFETs. However, they involve a problem that a hot carrier effect occurs.
In other words, where the above-mentioned conventional methods are used for solving the short channel effect, a high electric field occurs at edge portions of a gate electrode formed, thereby causing a generation of hot carriers. These hot carriers serve to degrade an operation characteristic of a MOSFET fabricated and reduce the use life of the MOSFET.
As another method for reducing the short channel effect, there have been also proposed a method of doping a bulk, namely, a substrate in a high concentration. However, this method involves a problem that a junction capacitance in source/drain regions increases due to the high impurity concentration. This is because the junction capacitance in the source/drain region of MOSFET is proportional to the impurity concentration.
In designing submicron MOSFETs, therefore, it is important to basically solve both the short channel effect and the hot carrier effect.
For solving both the short channel effect and the hot carrier effect, MOSFETs having various structures have been proposed.
For example, a lightly doped drain (LDD) MOSFET has been proposed in which a drain region has a double structure including a highly doped impurity region and a lightly doped impurity region disposed adjacent to the highly doped impurity region so as to reduce a hot carrier effect occurring in a MOSFET having a channel length of 1 .mu.m.
For improving such a LDD MOSFET, there have been also proposed a double implanted-LDD (DI-LDD) which is adapted to maintain a punch-through and improve a threshold in a MOSFET having a channel length of about 0.6 .mu.m.
FIG. 1 illustrates a sectional structure of a conventional DI-LDD MOSFET.
As shown in FIG. 1, the DI-LDD MOSFET includes source/drain regions constituted by n.sup.+ type regions 14 and 15 and n type regions 16 and 17 formed in a substrate 11, and a gate insulating film 12 and a gate film 13 formed over a channel region, as in a well-known LDD MOSFET structure. The DI-LDD MOSFET further includes p type regions 18 and 19 surrounding the source/drain regions.
In the DI-LDD MOSFET, the p type halo region 18 surrounds the n.sup.+ type region 14 and the n type region 16 constituting the source region, whereas the p type halo region 19 surrounds the n.sup.+ type region 15 and the n type region 17 constituting the drain region. Accordingly, the DI-LDD MOSFET has a symmetry in structure. Furthermore, the DI-LDD MOSFET has an electrically symmetric operation characteristic.
In this DI-LDD MOSFET, however, the p type halo regions 18 and 19 serving as punch-through stoppers should have a higher impurity concentration at a smaller channel length so as to maintain a punch-through.
This results in an increase in electric field occurring in the drain region and thereby degradations in breakdown characteristic and hot carrier reliability. As a result, there is a problem that the DI-LDD structure can not be employed in a MOSFET having a channel length of no more than 0.25 .mu.m (namely, sub-quarter micron).
Moreover, the increased impurity concentration in the p type halo regions 18 and 19 respectively surrounding the source and drain regions results in an increase in junction capacitance of the source/drain regions and thereby a degradation in operation characteristic of the device.
Recently, there have been proposed an asymmetry halo source gate-overlapped LDD (HS-GOLD) MOSFET which includes a gate-overlapped LDD formed at a drain region, and a halo region formed at a source region and having an opposite conductivity to the source region. Such an asymmetry HS-GOLD MOSFET is disclosed by Buti et al., IEEE Trans. on Electron Device, Vol. 38, No. 8, pp 1757.about.1764, 1991.
FIGS. 2A and 2B are sectional views illustrating a method for manufacturing a conventional asymmetry HS-GOLD MOSFET. In accordance with the illustrated method, ions are implanted in a p type substrate 21 so as to adjust a threshold voltage V.sub.T. Thereafter, a gate oxide film 22 is formed over the substrate 21. Over the gate oxide film 22, a polysilicon film is deposited which is, in turn, subjected to a patterning to form a gate 23. A CVD oxide film 24 is deposited to a small thickness over the entire exposed surface of the resulting structure.
Subsequently, n type impurity ions are implanted at a large tilt angle .phi. in the substrate 21 by use of a large tilt implantation process so as to a n type large-tilt implanted drain region 25. In similar, p type impurity ions are implanted in the substrate 21 at a large tilt angle .alpha. by use of the large tilt implantation process so as to a p type halo region 26 (FIG. 2A).
Over the entire exposed surface of the resulting structure, an oxide film is then formed. The oxide film is subjected to an anisotropic etch process so as to form spacers 27 at respective side walls of the gate 23.
Thereafter, n type impurity ions are implanted in the substrate 21 in a high concentration by use of a well-known ion implantation process, thereby forming an n.sup.+ region 28 as a drain region and a n.sup.+ region 29 as a source region. A formation of a tungsten silicide (TiSi.sub.2) 30 is achieved (FIG. 2B).
In this asymmetry HS-GOLD MOSFET in which its source region has the p type halo region 26 as a punch-through stopper whereas its drain region has a well-known LDD structure, an electrical asymmetry structure doping profile of the source/drain regions can be optimized so that both the punch-through resistance and the hot carrier reliability can be satisfied.
Since unnecessary LDD structures are omitted from the source region, it is possible to reduce the series resistance and the overlap capacitance of the source region. In addition, no provision of any p type halo region in the drain region makes it possible to reduce the junction capacitance of the drain region and thus improve a circuit operation capacity.
FIGS. 3 to 5 illustrate various characteristics of the conventional asymmetry HS-GOLD MOSFET, respectively.
FIG. 3 shows a superior saturation threshold (V.sub.Tsat) characteristic. Referring to FIGS. 4 and 5, it can be found that V.sub.DSmax (I.sub.sub =1 V/.mu.m) is higher than those of other conventional structures by about 0.7 V.
However, the large tilt implantation process used for fabricating the conventional asymmetry HS-GOLD MOSFET can be only employed in fabrication of transistors which are arranged in one direction on a wafer. This process can not be employed in fabrication of transistors optionally arranged.
Where the large tilt implantation process is employed, there is a limitation on the number of transistors packed because the transistors are arranged in one direction on a wafer. As a result, a considerable decrease in packing density is encountered in practical fabrication of VLSI.